The present invention relates generally to semiconductor devices, and more particularly to a high voltage wordline driver circuit implemented with a three stage level shifter for reducing high voltage stress conditions on transistor devices contained within the high voltage wordline driver circuit.
High voltage wordline driver circuits are used to apply voltages to the program/read gates of floating-gate transistors in integrated circuit (IC) memory cell arrays. When operated in a program mode, such drivers translate signals from integrated decoder circuits to signals, which must be of sufficiently high voltage to charge the floating gates. When operated in a read mode, the driver must provide a lower voltage signal having a rise-time sufficiently rapid enough to meet the operating speed requirements of the particular IC.
The task of constructing a driver circuit, in IC form, that not only is capable of furnishing the high voltage necessary for programming but also provides a rapid response time during the read operation, is difficult because driver transistors fabricated in IC form for high voltage (HV) use must have relatively long source-drain channels. The relatively long source-drain channels result in high capacitance characteristics that slow response time and decrease drive capability.
Conventional HV wordline driver circuits are typically comprised of a two-stage voltage level shifter. The first stage is a logic stage that translates signals from an integrated decoder circuit to signals necessary to drive the HV driver second stage. The logic stage operates at an operating voltage (VDD), which is typically less than 5VDC, and ground (GND). The second stage is the high-level driver stage that also acts as a voltage level shifter. The second stage input operates between 5VDC and GND while the second stage output typically produces either a low voltage (LV) of approximately 5VDC or less, or HV, which is a programming voltage typically greater than 12VDC. Because of this large level shifting between GND and more than 12VDC in the driver stage, conventional high voltage wordline driver circuits may experience driver transistor device stress caused by application of a HV that exceeds the transistor device's breakdown voltage. This condition can cause gated or punch through stress on the transistor device.
The use of high voltage NMOS and PMOS transistors is a potential solution to reduce the device stress. However, as explained above, HV transistors have a long source-drain channel that may slow the wordline drivers response time to the point where it may not meet the IC's operating speed requirements. A second potential solution is the use of a cascode driver structure. A cascode structure is a circuit structure in which typically two or more transistors are connected serially (they can be referred to as cascoded transistors). However, this solution adversely affects the slew rate (speed) of the wordline driver. Some conventional HV wordline driver circuits utilize a lifted ground, or floating ground, solution, but this concept results in variations of the ground level reference.
Therefore, desirable in the art of high voltage wordline driver circuits are improved circuit designs that eliminate the transistor device voltage stress condition without a cascode structure.